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foundatonise
- WATCHVER is a top level Verilog type project of a Stop Watch. DESIGN TYPE: Foundation ISE (chip V50 BG256 -6) -WATCHVER is a top level Verilog type project of a Stop Watch. DESIGN TYPE: Foundation ISE (chip V50 BG256-6)
data_check_hand_in
- 一个基于状态机的8位码流检测实现，Verilog语言，在ISE 10.1环境下编译通过。-A state machine-based 8-bit code stream detection to achieve, Verilog language, the ISE 10.1 environment compile.
pseudo-randomcodegenerator
- VERILOG语言编写的伪随机码产生器，可以ISE中编绎调试-VERILOG language of pseudo-random code generator, you can unravel ISE in debugging code
clock
- XPS做时钟的配置过程基于EXCD-1开发板,其实是基于xilinx的ISE来开发的，但是开发环境没有这个就这能选VHDL，另外是verilog的，呵呵。希望大家能够真正用上，挺好的“基于ISE的时钟”-XPS to do the configuration process is based on the clock EXCD-1 development board, in fact, is based on the xilinx the ISE to develop, but not the
Leg8
- 待商业化的8位高速cpu芯片设计，verilog语言编译通过，ISE平台完成-To be commercial cpu 8-bit high-speed chip design, verilog language compiler, ISE platform to complete
finial_test
- 卷积码和Viterbi译码的源程序，在Xilinx ISE环境下使用Verilog编写，有助于卷积码和Viterbi译码的学习-Convolutional codes and Viterbi decoding of the source, in the Xilinx ISE environment, use of Verilog prepared to help convolutional codes and Viterbi decoding of the study
Mux4
- Mux is designed by verilog use ISE of xilinx.have 4 input
adder_32bit
- 以ISE为平台，用Verilog编写的32位全加器模块，只需在Top模块中调用即可-The ISE as a platform, written with Verilog 32-bit full adder module, simply call the module to Top
i2c
- verilog语言实现i2c，在ise中调试仿真-verilog language i2c, debugging simulation in ise
counter
- 本文介绍了基于FPGA的数字频率计的设计方法，设计采用硬件描述语言Verilog ，在软件开发平台ISE上完成，可以在较高速时钟频率（48MHz）下正常工作。该数字频率计采用测频的方法，能准确的测量频率在10Hz到100MHz之间的信号。-This article describes the FPGA-based digital frequency meter design method using hardware descr iption language Verilog, ISE on t
top
- 在ISE环境里，用verilog语言编写得数码管显示程序，能动态计数-In the ISE environment, use the verilog language digital display program was able to dynamically count
AMI
- 在ISE软件环境下，用Verilog HDL语言实现通信中的AMI码的编码和译码，并有仿真波形。-In the ISE software environment, using Verilog HDL language for communication in the AMI code encoding and decoding, and a simulation waveform.
shuzipaobiao
- 在ISE环境下用Verilog HDL写的一个简易的数字跑表，最大量程为60分钟，精确到毫秒级，有复位键和暂停键。-In the ISE environment, using Verilog HDL to write a simple digital stopwatch, the maximum range is 60 minutes, accurate to the millisecond, the reset button and pause button.
traffic-light-FSM
- 在ISE环境下用Verilog代码分别用一段式和三段式来实现交通灯，并产生仿真波形。-In the ISE environment, were used in Verilog code to implement a three-stage type and traffic lights, and generate the simulation waveforms.
can-bus
- CAN总线控制器的VERILOG工程文件,很实用，工程是ISE可以打开，也可以只使用工程里面的代码-can bus project with VERILOG
DDS
- 在ISE环境中，运用verilog语言实现DDS（直接数字式频率合成器（Direct Digital Synthesizer）的英文缩写）的功能-In the ISE environment, use verilog language DDS (direct digital frequency synthesizer (Direct Digital Synthesizer) in abbreviation) of the function
verilog_lab_solution
- Verilog 实验代码。。。经典的，里面都是完整的项目文件。 ISE环境。-Verilog test code. . . Classic, which is a complete project file. ISE environment.
usb_latest.tar
- USB 源码。Verilog实现的USB程序，用ISE打开工程文件即可-USB verilog code。-Verilog implementation USB program, open the project file with the ISE can be
filer_pipeline
- 基于流水线的滤波器的设计与实现，verilog代码，xilinx，ISE，-Based on the assembly line of the design and realization of the filter, verilog code, xilinx, ISE,
sincount
- 用verilog语言开发的，ise产生正弦波的工程文件-Ise generate the triangular wave file